In a memory-mapped system initiators such as CPUs, GPUs, or other agents operate by reading and writing bytes of data in a target memory. Some agents are highly penalized by the latency to actually get access to their data. A usual approach is then for them to use a local-transient copy of a subset of the data, named a cache. As soon as a cache is present in a system, the system must ensure that no data is written in the memory target while some henceforth obsolete data still resides in that cache. The mechanism to ensure this property is called cache-coherency.
In a system where the various logic components may be designed by different teams, potentially in different companies, it is important to formalize the way cache-coherency information is exchanged. On a system on chip, the following protocols include Cache-Coherency: Open Core Protocol (OCP) 3.0, promoted by OCP International Partnership, and Advanced Microcontroller Bus Architecture (AMBA) Advanced eXtensible Interface (AXI) Coherency Extensions (ACE), promoted by ARM. Between integrated circuits, other protocols have been proposed: FSB (Front Side Bus, promoted by Intel), QPI (Intel Quick Path, promoted by Intel), and HyperTransport (promoted by the HyperTransport Consortium).
Protocols in general and Cache-Coherency protocols in particular have direct or indirect consequences on the logic blocks implementing them. Among other aspects are:
1) the amount of logic gates required to fulfill the protocol requirements
2) the complexity of this logic, impeding the maximum reachable frequency
3) the ability to cope with delays induced by the spreading of the various agents across the silicon die.
4) the architectural performance of the system.
5) the risk of design bugs